This invention addresses the problem of testing complex digital integrated circuits. Many families of integrated circuits fall into the category known as ASICs. The most prolific of these is known as Gate Arrays. Gate Arrays are usually prefabricated up to a certain stage (typically through all steps except metalization). The metal patterns are then configured according to the needs of the user's application. For these types of ASICs, it is necessary to test the circuit after the fabrication process is completed to insure the integrity of the circuit.
Today, virtually all such testing is done by applying a stream of test vectors to the integrated circuit device. A test vector is a pattern of signal values, some of which are applied to the integrated circuit device, and some of which represent an expected response from the integrated circuit device. The important point is that these vectors are applied to the periphery of the integrated circuit device, in a sequence which corresponds to a proper operational sequence of the integrated circuit device's internal circuitry. Most important is that this stream of vectors must be created and that the burden of this tedious task almost always falls on the user himself.
There have been many attempts to provide software which creates these vectors automatically. Unfortunately, none of these attempts have produced a solution which works for the majority of user applications. Automated solutions which functionally exercise a circuit work best when the user's application is implemented in regular, synchronous circuits. To further automate the testing of such synchronous designs, engineers have often added test circuitry to integrated circuits which is known as "scan test" circuitry, also known as "LSSD" and "boundary scan" circuitry. Examples of this type of test circuit are many, and include U.S. Pat. No. 4,488,259 to Mercy, U.S. Pat. No. 4,441,075 to McMahon, U.S. Pat. No. 4,780,874 to Lenoski, and U.S. Pat. No. 4,682,329 to Kluth, among others.
Scan test structures rely on stages of registers placed between blocks of combinatorial logic where extra circuitry has been added to allow the register contents to be shifted either in or out to allow the initialization or observation of logic states during testing. Unfortunately, a great many engineers don't design fully synchronous circuits where this type of structure can be used.
Attempts have also been made to add various forms of imbedded test circuitry aimed at testing integrated circuits regardless of what design style was employed by the designer. One of these is shown in U.S. Pat. No. 4,739,250 to Tanizawa where a gate array comprised of logic cells has a separate access circuit attached to an input of each logic cell, this access circuit being able to force a specific logic value at the output of the logic cell under control of row and column selection wires. This scheme can test every logic cell and connection, but only if they are of the simple NAND or NOR variety. It cannot arbitrarily apply any pattern to the inputs of all logic cells due to the limitation of the row and column addressing which controls the access circuits which, in turn, drive the test input of each logic cell. While it is possible to construct a gate array which uses simple NAND or NOR gates as the logic cell, a more complex logic cell is generally more effective when test circuitry is to be added on a per-cell basis.
Another test circuit which is intended for integrated circuits which may use either synchronous or non-synchronous designs is shown in U.S. Pat. No. 4,749,947 to Gheewala. This approach adds a row and column grid which connects to transistor pass-gates to selectively observe or drive a net in the user's circuit. This circuit is intended primarily to provide complete observability when used in conjunction with automatic test vector generation software. It has a limited ability to drive signals in the circuit, again due to limitations inherent in row and column addressing. As with the previous example, this test architecture cannot arbitrarily apply any pattern to the inputs of all logic cells.
Yet another example of prior art test circuits is U.S. Pat. No. 4,752,729 to Jackson. Although this circuit appears to be intended mostly for applying patterns useful for life-testing a device, its technique has some application in general circuit test. Here, interface circuits are inserted at various points within an integrated circuit. Each interface circuit controls the value of the logic signal which passes through the particular net under control of test signals which come from the exterior of the device and are connected in common to all interface circuits. Interface circuits can allow a signal simply to pass through or alternately to be forced to a logic "1" or "0" value. It is important to note that since all interface circuits follow the same test signals, it is impossible to use this scheme for applying any arbitrary pattern to any logic circuit within the integrated circuit.
Each of the imbedded test circuits in the last three examples has some ability to test an integrated circuit device regardless of whether the designer chose synchronous or asynchronous design techniques. However, none of these can fully control all the inputs of an internal circuit simultaneously and thus test that circuit by applying any arbitrary pattern to its inputs. It is this controllability that has been lacking and thus prevented an integrated circuit to be fully tested for all possible design implementations, using an imbedded test circuit.